The present invention relates generally to microprocessors and, more specifically, to microprocessors having encapsulated conductive lines, air as a dielectric between those lines, or both encapsulated conductive lines and air as a dielectric. The present invention also relates to a process for the manufacture of such microprocessors.
As semiconductor microprocessor circuit densities increase, dimensions are continuously being reduced. One challenge presented by this reduction is finding materials with a low dielectric constant that can be used between the metal lines or structures that comprise the various levels of a semiconductor circuit. As the dielectric constant of such materials is decreased, the speed of performance of the semiconductor product is increased. The theoretical minimum dielectric constant is E=1 (vacuum).
The dielectric constant is an important consideration, because the capacitance between current-carrying metal lines increases as circuit densities increase. Capacitance in semiconductor passive wiring can be estimated by a simple parallel plate capacitor equation:
C=Exc3x97A/D,
in which
C=capacitance;
E=the dielectric constant of the material between capacitor plates relative to the dielectric constant in a vacuum;
A=the area of the capacitor; and
D=the distance separating the plates of the capacitor.
The capacitance of a circuit affects the speed of a device. Speed is dependent on the product (RC) of the resistance (R) and the capacitance (C), known as the xe2x80x9cRC time constant.xe2x80x9d As the capacitance increases, the time constant increases, and therefore the circuit slows down.
Referring now to FIGS. 1 and 2, there is shown an exemplary semiconductor circuit having metal lines 510 and 512 with a distance xe2x80x9cDxe2x80x9d between the metal lines 510 and 512. As circuit densities increase, the distance D decreases to a value that may be less than 1 xcexcm. The area xe2x80x9cAxe2x80x9d (not shown) is the area of the line, bounded by the line height xe2x80x9cHxe2x80x9d and the line length xe2x80x9cL,xe2x80x9d and is typically in units of square microns. E (not shown) is the dielectric constant of the material 514 separating the two metal lines 510 and 512. If the material 514 is silicon dioxide, a material typically used in the art, the dielectric constant E is approximately 4.2. As circuit densities increase, it is desirable to counteract the decrease in the distance D with a decrease in the dielectric constant E, so that the capacitance C can be minimized.
It is also known in the semiconductor industry to apply an adhesion-promotion layer such as silicon oxide, silicon nitride, titanium, tungsten, or related compounds, before a metal deposition. The adhesion-promotion layer is often used as a barrier for metal migration. Typical methods of application for adhesion-promotion or barrier layers, however, only cover five out of the six surfaces of a three-dimensional trough or metal line.
The deficiencies of the conventional microprocessors and semiconductor processes used to manufacture such devices show that a need still exists for an improved microprocessor and process of manufacture. To overcome the shortcomings of the conventional devices and processes of manufacture, a new microprocessor and process of manufacture are provided. An object of the present invention is to create three-dimensional, multi-level semiconductor circuits using air as the dielectric material. A related object is to overcome the conventional problems (e.g., air is not a load-bearing substance like other dielectrics) which have prevented use of air as a dielectric material in semiconductor processes.
Still another object of the present invention is to provide a process which can be completed without destroying the structure during manufacturing. A more specific object is to avoid deterioration of the conductive metals, such as copper, used to form conductive lines. Yet another object is to prevent metal migration during anneal process steps.
It is another object of the present invention to encapsulate all six surfaces of a three-dimensional trough or metal line. In addition, a related object for the encapsulation process of the present invention is to provide for the top surface of the encapsulating layer to be planar with the top surface of surrounding fill.
To achieve these and other objects, and in view of its purposes, the present invention provides a process for manufacturing a microprocessor. The process comprises creating a plurality of adjacent structures having a solid fill between the structures; creating one or more layers above the structures and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between the adjacent structures.
In accordance with the present invention, there is also provided a process for manufacturing a microprocessor on a substrate, the process comprising the steps of:
a) creating a plurality of conductive lines having fill between the lines, each line having a top surface and one or more lower adhesion-promotion barrier layers underneath and between each line and the fill adjacent to the line, and the fill having a top surface;
b) expanding the fill to raise the fill top surface higher than the conductive line top surface;
c) applying one or more upper adhesion-promotion barrier layers over the fill top surface and over the conductive line top surface; and
d) removing the upper adhesion-promotion barrier layers except over the conductive line top surface, leaving each conductive line encapsulated by the upper and lower adhesion-promotion barrier layers.
The above processes may be combined to produce a multi-layer semiconductor circuit comprising conductive lines having air as a dielectric between the lines. Each line has six sides and each side is encapsulated by an adhesion-promotion barrier layer. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.